LOM=NORMAL_THE_CAN_CONT, TM=DISABLED_NORMAL_OPE, RPM=LOW_ACTIVE_RD_INPUT, RM=NORMAL_THE_CAN_CONTR, TPM=CAN_ID_THE_TRANSMIT, SM=WAKE_UP_NORMAL_OPER, STM=NORMAL_A_TRANSMITTE
Controls the operating mode of the CAN Controller.
| RM | Reset Mode. 0 (NORMAL_THE_CAN_CONTR): Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written. 1 (RESET_CAN_OPERATION): Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted. |
| LOM | Listen Only Mode. 0 (NORMAL_THE_CAN_CONT): Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value. 1 (LISTEN_ONLY_THE_CON): Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging. |
| STM | Self Test Mode. 0 (NORMAL_A_TRANSMITTE): Normal. A transmitted message must be acknowledged to be considered successful. 1 (SELF_TEST_THE_CONTR): Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR. |
| TPM | Transmit Priority Mode. 0 (CAN_ID_THE_TRANSMIT): CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier. 1 (LOCAL_PRIORITY_THE_): Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer. |
| SM | Sleep Mode. 0 (WAKE_UP_NORMAL_OPER): Wake-up. Normal operation. 1 (SLEEP_THE_CAN_CONTR): Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565. |
| RPM | Receive Polarity Mode. 0 (LOW_ACTIVE_RD_INPUT): Low active. RD input is active Low (dominant bit = 0). 1 (HIGH_ACTIVE_RD_INPU): High active. RD input is active High (dominant bit = 1) – reverse polarity. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| TM | Test Mode. 0 (DISABLED_NORMAL_OPE): Disabled. Normal operation. 1 (ENABLED_THE_TD_PIN_): Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |